; generated by Component: ARM Compiler 5.05 update 2 (build 169) Tool: ArmCC [4d0f38]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\main.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\main.d --cpu=Cortex-M4.fp --apcs=interwork -O0 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\M451Series\Include -I..\..\..\Library\StdDriver\inc -I..\Bsp -I..\User -I..\lcd_driver -I.\RTE\_project -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\4.3.0\CMSIS\Include -IDevice\M451\Include -D__UVISION_VERSION=527 -D_RTE_ --omf_browse=.\obj\main.crf ..\User\main.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  I2C0_IRQHandler PROC
;;;38     /*----------------------------------------------------------------------------*/
;;;39     void I2C0_IRQHandler(void)
000000  b510              PUSH     {r4,lr}
;;;40     {
;;;41     	unsigned int status;
;;;42     
;;;43     	status = I2C_GET_STATUS(I2C0);
000002  48bf              LDR      r0,|L1.768|
000004  68c4              LDR      r4,[r0,#0xc]
;;;44     	if(I2C_GET_TIMEOUT_FLAG(I2C0))
000006  6940              LDR      r0,[r0,#0x14]
000008  f0000001          AND      r0,r0,#1
00000c  b118              CBZ      r0,|L1.22|
;;;45     	{
;;;46     		/* Clear I2C0 Timeout Flag */
;;;47     		I2C_ClearTimeoutFlag(I2C0);
00000e  48bc              LDR      r0,|L1.768|
000010  f7fffffe          BL       I2C_ClearTimeoutFlag
000014  e006              B        |L1.36|
                  |L1.22|
;;;48     	}
;;;49     	else
;;;50     	{
;;;51     		if(i2c0handlerflag != NULL)
000016  48bb              LDR      r0,|L1.772|
000018  6800              LDR      r0,[r0,#0]  ; i2c0handlerflag
00001a  b118              CBZ      r0,|L1.36|
;;;52     			i2c0handlerflag(status);
00001c  4620              MOV      r0,r4
00001e  49b9              LDR      r1,|L1.772|
000020  6809              LDR      r1,[r1,#0]  ; i2c0handlerflag
000022  4788              BLX      r1
                  |L1.36|
;;;53     	}
;;;54     }
000024  bd10              POP      {r4,pc}
;;;55     /*----------------------------------------------------------------------------*/
                          ENDP

                  I2C_MasterRx PROC
;;;57     /*----------------------------------------------------------------------------*/
;;;58     void I2C_MasterRx(unsigned int rxstatus)
000026  b510              PUSH     {r4,lr}
;;;59     {
000028  4604              MOV      r4,r0
;;;60     	if(rxstatus == 0x08)                       	/* START has been transmitted and prepare SLA+W */
00002a  2c08              CMP      r4,#8
00002c  d10a              BNE      |L1.68|
;;;61     	{
;;;62     		I2C_SET_DATA(I2C0, (VKL280_ADDR << 1)); /* Write SLA+W to Register I2CDAT */
00002e  207c              MOVS     r0,#0x7c
000030  49b3              LDR      r1,|L1.768|
000032  6088              STR      r0,[r1,#8]
;;;63     		I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);		
000034  4608              MOV      r0,r1
000036  6800              LDR      r0,[r0,#0]
000038  f020003c          BIC      r0,r0,#0x3c
00003c  f0400008          ORR      r0,r0,#8
000040  6008              STR      r0,[r1,#0]
000042  e055              B        |L1.240|
                  |L1.68|
;;;64     	}
;;;65     	else if(rxstatus == 0x18)                   /* SLA+W has been transmitted and ACK has been received */
000044  2c18              CMP      r4,#0x18
000046  d111              BNE      |L1.108|
;;;66     	{
;;;67     		I2C_SET_DATA(I2C0, i2crdtx[txcnt++]);
000048  48af              LDR      r0,|L1.776|
00004a  7801              LDRB     r1,[r0,#0]  ; txcnt
00004c  7800              LDRB     r0,[r0,#0]  ; txcnt
00004e  1c40              ADDS     r0,r0,#1
000050  4aad              LDR      r2,|L1.776|
000052  7010              STRB     r0,[r2,#0]
000054  48ad              LDR      r0,|L1.780|
000056  5c40              LDRB     r0,[r0,r1]
000058  49a9              LDR      r1,|L1.768|
00005a  6088              STR      r0,[r1,#8]
;;;68     		I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);		
00005c  4608              MOV      r0,r1
00005e  6800              LDR      r0,[r0,#0]
000060  f020003c          BIC      r0,r0,#0x3c
000064  f0400008          ORR      r0,r0,#8
000068  6008              STR      r0,[r1,#0]
00006a  e041              B        |L1.240|
                  |L1.108|
;;;69     	}
;;;70     	else if(rxstatus == 0x20)                   /* SLA+W has been transmitted and NACK has been received */
00006c  2c20              CMP      r4,#0x20
00006e  d10b              BNE      |L1.136|
;;;71     	{
;;;72     		I2C_STOP(I2C0);
000070  48a3              LDR      r0,|L1.768|
000072  f7fffffe          BL       I2C_STOP
;;;73     		I2C_START(I2C0);
000076  48a2              LDR      r0,|L1.768|
000078  6800              LDR      r0,[r0,#0]
00007a  f0200008          BIC      r0,r0,#8
00007e  f0400020          ORR      r0,r0,#0x20
000082  499f              LDR      r1,|L1.768|
000084  6008              STR      r0,[r1,#0]
000086  e033              B        |L1.240|
                  |L1.136|
;;;74     	}
;;;75     	else if(rxstatus == 0x28)                   /* DATA has been transmitted and ACK has been received */
000088  2c28              CMP      r4,#0x28
00008a  d108              BNE      |L1.158|
;;;76     	{
;;;77     		I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STA_SI);  //ݡSR START
00008c  489c              LDR      r0,|L1.768|
00008e  6800              LDR      r0,[r0,#0]
000090  f020003c          BIC      r0,r0,#0x3c
000094  f0400028          ORR      r0,r0,#0x28
000098  4999              LDR      r1,|L1.768|
00009a  6008              STR      r0,[r1,#0]
00009c  e028              B        |L1.240|
                  |L1.158|
;;;78     	}
;;;79     	else if(rxstatus == 0x10)                   /* Repeat START has been transmitted and prepare SLA+R */
00009e  2c10              CMP      r4,#0x10
0000a0  d10a              BNE      |L1.184|
;;;80     	{
;;;81     		I2C_SET_DATA(I2C0, ((VKL280_ADDR << 1) | 0x01));   /* Write SLA+R to Register I2CDAT */
0000a2  207d              MOVS     r0,#0x7d
0000a4  4996              LDR      r1,|L1.768|
0000a6  6088              STR      r0,[r1,#8]
;;;82     	I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);		  
0000a8  4608              MOV      r0,r1
0000aa  6800              LDR      r0,[r0,#0]
0000ac  f020003c          BIC      r0,r0,#0x3c
0000b0  f0400008          ORR      r0,r0,#8
0000b4  6008              STR      r0,[r1,#0]
0000b6  e01b              B        |L1.240|
                  |L1.184|
;;;83     	}
;;;84     	else if(rxstatus == 0x40)                   /* SLA+R has been transmitted and ACK has been received */
0000b8  2c40              CMP      r4,#0x40
0000ba  d108              BNE      |L1.206|
;;;85     	{
;;;86     		I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
0000bc  4890              LDR      r0,|L1.768|
0000be  6800              LDR      r0,[r0,#0]
0000c0  f020003c          BIC      r0,r0,#0x3c
0000c4  f0400008          ORR      r0,r0,#8
0000c8  498d              LDR      r1,|L1.768|
0000ca  6008              STR      r0,[r1,#0]
0000cc  e010              B        |L1.240|
                  |L1.206|
;;;87     	}
;;;88     	else if(rxstatus == 0x58)                   /* DATA has been received and NACK has been returned */
0000ce  2c58              CMP      r4,#0x58
0000d0  d10e              BNE      |L1.240|
;;;89     	{
;;;90     	i2crdrx = (unsigned char) I2C_GET_DATA(I2C0);
0000d2  488b              LDR      r0,|L1.768|
0000d4  6880              LDR      r0,[r0,#8]
0000d6  498e              LDR      r1,|L1.784|
0000d8  7008              STRB     r0,[r1,#0]
;;;91     	I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STO_SI);  //STOP
0000da  4889              LDR      r0,|L1.768|
0000dc  6800              LDR      r0,[r0,#0]
0000de  f020003c          BIC      r0,r0,#0x3c
0000e2  f0400018          ORR      r0,r0,#0x18
0000e6  4986              LDR      r1,|L1.768|
0000e8  6008              STR      r0,[r1,#0]
;;;92     	endflag = 1;
0000ea  2001              MOVS     r0,#1
0000ec  4989              LDR      r1,|L1.788|
0000ee  7008              STRB     r0,[r1,#0]
                  |L1.240|
;;;93     	} 
;;;94     	else
;;;95     	{
;;;96     		/* TO DO */
;;;97     		//rxstatusis NOT processed
;;;98     	}
;;;99     }
0000f0  bd10              POP      {r4,pc}
;;;100    /*----------------------------------------------------------------------------*/
                          ENDP

                  I2C_MasterTx PROC
;;;102    /*----------------------------------------------------------------------------*/
;;;103    void I2C_MasterTx(unsigned int txstatus)
0000f2  b510              PUSH     {r4,lr}
;;;104    {
0000f4  4604              MOV      r4,r0
;;;105    	if(txstatus == 0x08)                        /* START has been transmitted */
0000f6  2c08              CMP      r4,#8
0000f8  d10a              BNE      |L1.272|
;;;106    	{
;;;107    		I2C_SET_DATA(I2C0, VKL280_ADDR << 1);   /* Write SLA+W to Register I2CDAT */
0000fa  207c              MOVS     r0,#0x7c
0000fc  4980              LDR      r1,|L1.768|
0000fe  6088              STR      r0,[r1,#8]
;;;108    		I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
000100  4608              MOV      r0,r1
000102  6800              LDR      r0,[r0,#0]
000104  f020003c          BIC      r0,r0,#0x3c
000108  f0400008          ORR      r0,r0,#8
00010c  6008              STR      r0,[r1,#0]
00010e  e046              B        |L1.414|
                  |L1.272|
;;;109    	}
;;;110    	else if(txstatus == 0x18)                   /* SLA+W has been transmitted and ACK has been received */
000110  2c18              CMP      r4,#0x18
000112  d111              BNE      |L1.312|
;;;111    	{
;;;112    		I2C_SET_DATA(I2C0, i2cwrbuf[txcnt++]);
000114  487c              LDR      r0,|L1.776|
000116  7801              LDRB     r1,[r0,#0]  ; txcnt
000118  7800              LDRB     r0,[r0,#0]  ; txcnt
00011a  1c40              ADDS     r0,r0,#1
00011c  4a7a              LDR      r2,|L1.776|
00011e  7010              STRB     r0,[r2,#0]
000120  487d              LDR      r0,|L1.792|
000122  5c40              LDRB     r0,[r0,r1]
000124  4976              LDR      r1,|L1.768|
000126  6088              STR      r0,[r1,#8]
;;;113    		I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
000128  4608              MOV      r0,r1
00012a  6800              LDR      r0,[r0,#0]
00012c  f020003c          BIC      r0,r0,#0x3c
000130  f0400008          ORR      r0,r0,#8
000134  6008              STR      r0,[r1,#0]
000136  e032              B        |L1.414|
                  |L1.312|
;;;114    	}
;;;115    	else if(txstatus == 0x20)                   /* SLA+W has been transmitted and NACK has been received */
000138  2c20              CMP      r4,#0x20
00013a  d10b              BNE      |L1.340|
;;;116    	{
;;;117    		I2C_STOP(I2C0);
00013c  4870              LDR      r0,|L1.768|
00013e  f7fffffe          BL       I2C_STOP
;;;118    		I2C_START(I2C0);
000142  486f              LDR      r0,|L1.768|
000144  6800              LDR      r0,[r0,#0]
000146  f0200008          BIC      r0,r0,#8
00014a  f0400020          ORR      r0,r0,#0x20
00014e  496c              LDR      r1,|L1.768|
000150  6008              STR      r0,[r1,#0]
000152  e024              B        |L1.414|
                  |L1.340|
;;;119    	}
;;;120    	else if(txstatus == 0x28)                   /* DATA has been transmitted and ACK has been received */
000154  2c28              CMP      r4,#0x28
000156  d122              BNE      |L1.414|
;;;121    	{
;;;122    		if(txcnt != txlen)
000158  486b              LDR      r0,|L1.776|
00015a  7800              LDRB     r0,[r0,#0]  ; txcnt
00015c  496f              LDR      r1,|L1.796|
00015e  7809              LDRB     r1,[r1,#0]  ; txlen
000160  4288              CMP      r0,r1
000162  d011              BEQ      |L1.392|
;;;123    		{
;;;124    				I2C_SET_DATA(I2C0, i2cwrbuf[txcnt++]);
000164  4868              LDR      r0,|L1.776|
000166  7801              LDRB     r1,[r0,#0]  ; txcnt
000168  7800              LDRB     r0,[r0,#0]  ; txcnt
00016a  1c40              ADDS     r0,r0,#1
00016c  4a66              LDR      r2,|L1.776|
00016e  7010              STRB     r0,[r2,#0]
000170  4869              LDR      r0,|L1.792|
000172  5c40              LDRB     r0,[r0,r1]
000174  4962              LDR      r1,|L1.768|
000176  6088              STR      r0,[r1,#8]
;;;125    				I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
000178  4608              MOV      r0,r1
00017a  6800              LDR      r0,[r0,#0]
00017c  f020003c          BIC      r0,r0,#0x3c
000180  f0400008          ORR      r0,r0,#8
000184  6008              STR      r0,[r1,#0]
000186  e00a              B        |L1.414|
                  |L1.392|
;;;126    		}
;;;127    		else
;;;128    		{
;;;129    				I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STO_SI);
000188  485d              LDR      r0,|L1.768|
00018a  6800              LDR      r0,[r0,#0]
00018c  f020003c          BIC      r0,r0,#0x3c
000190  f0400018          ORR      r0,r0,#0x18
000194  495a              LDR      r1,|L1.768|
000196  6008              STR      r0,[r1,#0]
;;;130    				endflag = 1;
000198  2001              MOVS     r0,#1
00019a  495e              LDR      r1,|L1.788|
00019c  7008              STRB     r0,[r1,#0]
                  |L1.414|
;;;131    		}
;;;132    	}
;;;133    	else
;;;134    	{
;;;135    	 /* TO DO */
;;;136    	//txstatus is NOT processed
;;;137    	}
;;;138    }
00019e  bd10              POP      {r4,pc}
;;;139    
                          ENDP

                  loopshift_left8 PROC
;;;146    *******************************************************************************/
;;;147    unsigned char loopshift_left8(unsigned char dat)
0001a0  b510              PUSH     {r4,lr}
;;;148    {
0001a2  4601              MOV      r1,r0
;;;149    	unsigned char i,retval,datval;
;;;150    	
;;;151    	datval=dat;
0001a4  460a              MOV      r2,r1
;;;152    	retval=0;
0001a6  2000              MOVS     r0,#0
;;;153    	for(i=0;i<8;i++)
0001a8  2300              MOVS     r3,#0
0001aa  e00a              B        |L1.450|
                  |L1.428|
;;;154    	{
;;;155    		retval>>=1;
0001ac  1040              ASRS     r0,r0,#1
;;;156    		if((datval&0x80)==0x80)
0001ae  f0020480          AND      r4,r2,#0x80
0001b2  2c80              CMP      r4,#0x80
0001b4  d101              BNE      |L1.442|
;;;157    			retval|=0x80;
0001b6  f0400080          ORR      r0,r0,#0x80
                  |L1.442|
;;;158    		datval<<=1;
0001ba  0654              LSLS     r4,r2,#25
0001bc  0e22              LSRS     r2,r4,#24
0001be  1c5c              ADDS     r4,r3,#1              ;153
0001c0  b2e3              UXTB     r3,r4                 ;153
                  |L1.450|
0001c2  2b08              CMP      r3,#8                 ;153
0001c4  dbf2              BLT      |L1.428|
;;;159    	}
;;;160    	return retval;
;;;161    }
0001c6  bd10              POP      {r4,pc}
;;;162    /*******************************************************************************
                          ENDP

                  VKL280_I2C_WRDat PROC
;;;170    *******************************************************************************/
;;;171    void VKL280_I2C_WRDat(unsigned char Addr,unsigned char *Databuf,unsigned char cnt)
0001c8  b570              PUSH     {r4-r6,lr}
;;;172    {
0001ca  4603              MOV      r3,r0
;;;173    	unsigned char i;
;;;174    	
;;;175    	//ֽ0ʾramַ߰ramַINF־Ĵַ
;;;176    	i2cwrbuf[0] = Addr&0xff; 
0001cc  4d52              LDR      r5,|L1.792|
0001ce  702b              STRB     r3,[r5,#0]
;;;177    	for(i=0;i<cnt;i++)
0001d0  2000              MOVS     r0,#0
0001d2  e005              B        |L1.480|
                  |L1.468|
;;;178    	{
;;;179    //		i2cdatbuf[1+i] = loopshift_left8(*Databuf++);	//λ	
;;;180    		i2cwrbuf[1+i] = *Databuf++; 									//λ
0001d4  f8115b01          LDRB     r5,[r1],#1
0001d8  1c44              ADDS     r4,r0,#1
0001da  4e4f              LDR      r6,|L1.792|
0001dc  5535              STRB     r5,[r6,r4]
0001de  b2e0              UXTB     r0,r4                 ;177
                  |L1.480|
0001e0  4290              CMP      r0,r2                 ;177
0001e2  dbf7              BLT      |L1.468|
;;;181    	}
;;;182    	txcnt = 0;
0001e4  2400              MOVS     r4,#0
0001e6  4d48              LDR      r5,|L1.776|
0001e8  702c              STRB     r4,[r5,#0]
;;;183    	txlen=cnt+1;  //ֽ0ǵַ
0001ea  1c54              ADDS     r4,r2,#1
0001ec  4d4b              LDR      r5,|L1.796|
0001ee  702c              STRB     r4,[r5,#0]
;;;184    	endflag = 0;
0001f0  2400              MOVS     r4,#0
0001f2  4d48              LDR      r5,|L1.788|
0001f4  702c              STRB     r4,[r5,#0]
;;;185    
;;;186    	/* I2C function to write data to slave */
;;;187    	i2c0handlerflag = (I2C_FUNC)I2C_MasterTx;
0001f6  f2af1405          ADR      r4,I2C_MasterTx + 1
0001fa  4d42              LDR      r5,|L1.772|
0001fc  602c              STR      r4,[r5,#0]  ; i2c0handlerflag
;;;188    
;;;189    	/* I2C as master sends START signal */
;;;190    	I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STA);
0001fe  4c40              LDR      r4,|L1.768|
000200  6824              LDR      r4,[r4,#0]
000202  f024043c          BIC      r4,r4,#0x3c
000206  f0440420          ORR      r4,r4,#0x20
00020a  4d3d              LDR      r5,|L1.768|
00020c  602c              STR      r4,[r5,#0]
;;;191    
;;;192    	/* Wait I2C Tx Finish */
;;;193    	while(endflag == 0);
00020e  bf00              NOP      
                  |L1.528|
000210  4c40              LDR      r4,|L1.788|
000212  7824              LDRB     r4,[r4,#0]  ; endflag
000214  2c00              CMP      r4,#0
000216  d0fb              BEQ      |L1.528|
;;;194    	endflag = 0;
000218  2400              MOVS     r4,#0
00021a  4d3e              LDR      r5,|L1.788|
00021c  702c              STRB     r4,[r5,#0]
;;;195    }
00021e  bd70              POP      {r4-r6,pc}
;;;196    /*******************************************************************************
                          ENDP

                  VKL280_I2C_RDDat PROC
;;;204    *******************************************************************************/
;;;205    void VKL280_I2C_RDDat(unsigned char Addr,unsigned char *Databuf,unsigned char cnt)
000220  b570              PUSH     {r4-r6,lr}
;;;206    {	
000222  4603              MOV      r3,r0
;;;207    	unsigned char i,rxnum;
;;;208    
;;;209    	rxnum=cnt;
000224  4614              MOV      r4,r2
;;;210    	for(i=0;i<rxnum;i++)
000226  2000              MOVS     r0,#0
000228  e028              B        |L1.636|
                  |L1.554|
;;;211    	{
;;;212    		//I2C͵ַ
;;;213    		i2crdtx[0] = (Addr&0xff)+i;
00022a  181d              ADDS     r5,r3,r0
00022c  4e37              LDR      r6,|L1.780|
00022e  7035              STRB     r5,[r6,#0]
;;;214    		txcnt = 0;
000230  2500              MOVS     r5,#0
000232  4e35              LDR      r6,|L1.776|
000234  7035              STRB     r5,[r6,#0]
;;;215    		txlen=1;
000236  2501              MOVS     r5,#1
000238  4e38              LDR      r6,|L1.796|
00023a  7035              STRB     r5,[r6,#0]
;;;216    		endflag = 0;
00023c  2500              MOVS     r5,#0
00023e  4e35              LDR      r6,|L1.788|
000240  7035              STRB     r5,[r6,#0]
;;;217    		//I2C
;;;218    		/* I2C function to read data from slave */
;;;219    		i2c0handlerflag = (I2C_FUNC)I2C_MasterRx;
000242  f2af251d          ADR      r5,I2C_MasterRx + 1
000246  4e2f              LDR      r6,|L1.772|
000248  6035              STR      r5,[r6,#0]  ; i2c0handlerflag
;;;220    
;;;221    		rxcnt = 0;
00024a  2500              MOVS     r5,#0
00024c  4e34              LDR      r6,|L1.800|
00024e  7035              STRB     r5,[r6,#0]
;;;222    		rxlen=1;
000250  2501              MOVS     r5,#1
000252  4e34              LDR      r6,|L1.804|
000254  7035              STRB     r5,[r6,#0]
;;;223    
;;;224    		I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STA);
000256  4d2a              LDR      r5,|L1.768|
000258  682d              LDR      r5,[r5,#0]
00025a  f025053c          BIC      r5,r5,#0x3c
00025e  f0450520          ORR      r5,r5,#0x20
000262  4e27              LDR      r6,|L1.768|
000264  6035              STR      r5,[r6,#0]
;;;225    
;;;226    		/* Wait I2C Rx Finish */
;;;227    		while(endflag == 0);
000266  bf00              NOP      
                  |L1.616|
000268  4d2a              LDR      r5,|L1.788|
00026a  782d              LDRB     r5,[r5,#0]  ; endflag
00026c  2d00              CMP      r5,#0
00026e  d0fb              BEQ      |L1.616|
;;;228    		//*Databuf++=loopshift_left8(i2cdatbuf[txlen]); //λȶ
;;;229    		*Databuf++=i2crdrx; 
000270  4d27              LDR      r5,|L1.784|
000272  782d              LDRB     r5,[r5,#0]  ; i2crdrx
000274  f8015b01          STRB     r5,[r1],#1
000278  1c45              ADDS     r5,r0,#1              ;210
00027a  b2e8              UXTB     r0,r5                 ;210
                  |L1.636|
00027c  42a0              CMP      r0,r4                 ;210
00027e  dbd4              BLT      |L1.554|
;;;230    	}
;;;231    }
000280  bd70              POP      {r4-r6,pc}
;;;232    //ӲI2CϺI2C
                          ENDP

                  main PROC
;;;240    *******************************************************************************/
;;;241    int main(void)
000282  b510              PUSH     {r4,lr}
;;;242    {
;;;243    	//Ƭ
;;;244    	SYS_UnlockReg();	/* Unlock protected registers */
000284  bf00              NOP      
000286  bf00              NOP      
000288  bf00              NOP      
                  |L1.650|
00028a  2059              MOVS     r0,#0x59
00028c  4926              LDR      r1,|L1.808|
00028e  6008              STR      r0,[r1,#0]
000290  2016              MOVS     r0,#0x16
000292  0589              LSLS     r1,r1,#22
000294  f8c10100          STR      r0,[r1,#0x100]
000298  2088              MOVS     r0,#0x88
00029a  f8c10100          STR      r0,[r1,#0x100]
00029e  06c0              LSLS     r0,r0,#27
0002a0  f8d00100          LDR      r0,[r0,#0x100]
0002a4  2800              CMP      r0,#0
0002a6  d0f0              BEQ      |L1.650|
0002a8  bf00              NOP      
;;;245    	SYS_Init();	
0002aa  f7fffffe          BL       SYS_Init
;;;246    	SYS_LockReg();		/* Lock protected registers */
0002ae  bf00              NOP      
0002b0  2000              MOVS     r0,#0
0002b2  491d              LDR      r1,|L1.808|
0002b4  6008              STR      r0,[r1,#0]
0002b6  bf00              NOP      
;;;247    	
;;;248    	//ӲI2C䣬I2CΡ
;;;249    	/* Set I2C Slave Addresses */
;;;250    	I2C_SetSlaveAddr(I2C0, 0, VKL280_ADDR, 0);   /* Slave Address*/
0002b8  2300              MOVS     r3,#0
0002ba  223e              MOVS     r2,#0x3e
0002bc  4619              MOV      r1,r3
0002be  4810              LDR      r0,|L1.768|
0002c0  f7fffffe          BL       I2C_SetSlaveAddr
;;;251    	/* Enable I2C interrupt */
;;;252    	I2C_EnableInt(I2C0);
0002c4  480e              LDR      r0,|L1.768|
0002c6  f7fffffe          BL       I2C_EnableInt
;;;253    	NVIC_EnableIRQ(I2C0_IRQn);
0002ca  2026              MOVS     r0,#0x26
0002cc  f000021f          AND      r2,r0,#0x1f
0002d0  2101              MOVS     r1,#1
0002d2  4091              LSLS     r1,r1,r2
0002d4  0942              LSRS     r2,r0,#5
0002d6  0092              LSLS     r2,r2,#2
0002d8  f10222e0          ADD      r2,r2,#0xe000e000
0002dc  f8c21100          STR      r1,[r2,#0x100]
0002e0  bf00              NOP      
;;;254    	//ӲI2CϺI2C
;;;255    	
;;;256      //ò		
;;;257    	VKL280_Main();	
0002e2  f7fffffe          BL       VKL280_Main
;;;258    }	
0002e6  2000              MOVS     r0,#0
0002e8  bd10              POP      {r4,pc}
;;;259    /************************END OF FILE****/
                          ENDP

                  I2C_STOP PROC
;;;367     */
;;;368    static __INLINE void I2C_STOP(I2C_T *i2c)
0002ea  6801              LDR      r1,[r0,#0]
;;;369    {
;;;370    
;;;371        (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk);
0002ec  f0410118          ORR      r1,r1,#0x18
0002f0  6001              STR      r1,[r0,#0]
;;;372        while(i2c->CTL & I2C_CTL_STO_Msk);
0002f2  bf00              NOP      
                  |L1.756|
0002f4  6801              LDR      r1,[r0,#0]
0002f6  f0010110          AND      r1,r1,#0x10
0002fa  2900              CMP      r1,#0
0002fc  d1fa              BNE      |L1.756|
;;;373    }
0002fe  4770              BX       lr
;;;374    
                          ENDP

                  |L1.768|
                          DCD      0x40080000
                  |L1.772|
                          DCD      i2c0handlerflag
                  |L1.776|
                          DCD      txcnt
                  |L1.780|
                          DCD      i2crdtx
                  |L1.784|
                          DCD      i2crdrx
                  |L1.788|
                          DCD      endflag
                  |L1.792|
                          DCD      i2cwrbuf
                  |L1.796|
                          DCD      txlen
                  |L1.800|
                          DCD      rxcnt
                  |L1.804|
                          DCD      rxlen
                  |L1.808|
                          DCD      0x40000100

                          AREA ||.bss||, DATA, NOINIT, ALIGN=0

                  i2cwrbuf
                          %        64
                  i2crdtx
                          %        64

                          AREA ||.data||, DATA, ALIGN=2

                  i2c0handlerflag
                          DCD      0x00000000
                  i2crdrx
000004  00                DCB      0x00
                  txlen
000005  00                DCB      0x00
                  txcnt
000006  00                DCB      0x00
                  rxlen
000007  00                DCB      0x00
                  rxcnt
000008  00                DCB      0x00
                  endflag
000009  00                DCB      0x00

;*** Start embedded assembler ***

#line 1 "..\\User\\main.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___6_main_c_endflag____REV16|
#line 114 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___6_main_c_endflag____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___6_main_c_endflag____REVSH|
#line 128
|__asm___6_main_c_endflag____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***

                  __ARM_use_no_argv EQU 0
